cy22050 cy220501 one-pll general purpose flash programmable clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07006 rev. *f revised january 21, 2009 features integrated phase-locked loop (pll) commercial and industrial operation flash-programmable field-programmable low-skew, low-jitter, high-accuracy outputs 3.3v operation with 2.5v output option 16-pin tssop package (cy22050) 16-pin tssop package with nipdau lead finish (cy220501) benefits internal pll to generate six outputs up to 200 mhz. able to generate custom frequencies from an external reference crystal or driven source. performance guaranteed for appl ications that require an extended temperature range. reprogrammable technology allows easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. in-house programming of sample s and prototype quantities is available using the cy3672 ftg development kit. production quantities are available through cypress?s value-added distri- bution partners or by using third party programmers from bp microsystems, hilo systems, and others. high performance suited for commercial, industrial, networking, telecomm and other general-purpose applications. application compatibility in standard and low-power systems. industry standard packaging saves on board space. table 1. specifications part number outputs input frequency range output frequency range specifications cy22050fc 6 8 mhz?30 mhz (external crystal) 1 mhz?133 mhz (driven clock) 80 khz?200 mhz (3.3v) 80 khz?166.6 mhz (2.5v) field-programmable commercial temperature cy22050fi 6 8 mhz?30 mhz (external crystal) 1 mhz?133 mhz (driven clock) 80 khz?166.6 mhz (3.3v) 80 khz?150 mhz (2.5v) field-programmable industrial temperature xin xout divider pll osc. lclk3 q p vco vddl avss avdd vss lclk2 lclk4 clk5 clk6 vssl vdd bank 1 divider bank 2 output select oe pwrdwn lclk1 matrix logic block diagram [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 2 of 10 pin configuration figure 1. 16-pin tssop table 2. pin definitions name pin number description xin 1 reference input. driven by a crystal (8 mh z?30 mhz) or external clock (1 mhz?133 mhz). programmable input load capacitors allow for ma ximum flexibility in selecting a crystal, based on manufacturer, process, performance, or quality. vdd 2 3.3v voltage supply avdd 3 3.3v analog voltage supply pwrdwn [1] 4 power down. when pin 4 is driven low, the cy22050 goes into shut down mode. avss 5 analog ground vssl 6 lclk ground lclk1 7 configurable clock output 1 at v ddl level (3.3v or 2.5v) lclk2 8 configurable clock output 2 at v ddl level (3.3v or 2.5v) lclk3 9 configurable clock output 3 at v ddl level (3.3v or 2.5v) oe [1] 10 output enable. when pin 10 is driven low, all outputs are three-stated. vddl 11 lclk voltage supply (2.5v or 3.3v) lclk4 12 configurable clock output 4 at v ddl level (3.3v or 2.5v) vss 13 ground clk5 14 configurable clock output 5 (3.3v) clk6 15 configurable clock output 6 (3.3v) xout [2] 16 reference output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl oe lclk1 xin xout vdd pwrdwn avss lclk3 lclk2 clk6 clk5 avdd vddl lclk4 notes 1. the cy22050 has no internal pull up or pull down resistors. pwrdwn and oe pins need to be driven as appropriate or tied to power or ground. 2. float xout if xin is driven by an external clock source. [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 3 of 10 functional description the cy22050 is the next-generation programmable ftg (frequency timing generator) for use in networking, telecommunication, dataco m, and other general-purpose applications. the cy22050 offers up to six configurable outputs in a 16-pin tssop, running off a 3.3v power supply. the on-chip reference oscillator is designed to run off an 8?30-mhz crystal, or a 1?133-mhz external clock signal. the cy22050 has a single pll driving 6 programmable output clocks. the output clocks are derived from the pll or the reference frequency (ref). output post dividers are available for either. four of the outputs can be set as 3.3v or 2.5v, for use in a wide variety of portable and low-power applications. the cy220501 is the cy22050 with nipdau lead finish. field programming the cy22050f the cy22050 is programmed at the package level, that is, in a programmer socket. the cy22050 is flash-technology based, so the parts can be reprogrammed up to 100 times. this allows for fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. samples and small prototype q uantities can be programmed on the cy3672 programmer. cypress?s value-added distribution partners and third-party pr ogramming systems from bp micro- systems, hilo systems, and others are available for large-production quantities. cyclocksrt ? software cyclocksrt? is an easy-to-use so ftware applicat ion that allows the user to custom-configure the cy22050. users can specify the ref, pll frequency, output fr equencies and/or post-dividers, and different functional options. cyclocksr t outputs an industry-standard jedec file used for programming the cy22050. cyclocksrt can be do wnloaded free of charge from the cypress website at ht tp://www.cypress.com. cy3672 ftg development kit the cypress cy3672 ftg development kit comes complete with everything needed to desi gn with the cy22050 and program samples and small prototype quant ities. the kit comes with the latest version of cyclocksrt and a small portable programmer that connects to a pc serial port for on-the-fly programming of custom frequencies. the jedec file output of cycl ocksrt can be downloaded to the portable programmer for small-vo lume programming, or for use with a production programming system for larger volumes. applications controlling jitter jitter is defined in many ways, including: phase noise, long-term jitter, cycle-to-cycle jitter, period jit ter, absolute ji tter, and deter- ministic jitter. these jitter terms are usually given in terms of rms, peak-to-peak, or in the case of phase noise dbc/hz with respect to the fundamental frequency. actual jitter is dependent on xin jitter and edge rate, number of active outputs, output frequencies, v ddl (2.5v or 3.3v), temper ature, and output load. power supply noise and clock output loading are two major system sources of clock jitter. power supply noise can be mitigated by proper power supply decoupling (0.1- f ceramic cap) of the clock and ensuring a low-impedance ground to the chip. reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. reducing the total number of active outputs also reduce jitter in a linear fashion. however, it is better to use two outputs to drive two loads than one output to drive two loads. the rate and magnitude that the pll corrects the vco frequency is directly related to jitter perform ance. if the rate is too slow, then long term jitter and phase noise is poor. therefore, to improve long-term jitter and phase noise, reducing q to a minimum is advisable. this technique in creases the speed of the phase frequency detector, which in turn drives the input voltage of the vco. in a similar manner, increasing p until the vco is near its maximum rated speed also decreases long term jitter and phase noise. for example: input refer ence of 12 mhz; desired output frequency of 33.3 mhz. one mi ght arrive at the following solution: set q = 3, p = 25, post div = 3. however, the best jitter results are q = 2, p = 50, post div = 9. for additional information, refer to the application note, ?jitter in pll-based systems: causes, effects, and solutions,? available at http://www.cypress. com (click on ?application notes?), or contact your local cypress field applications engineer. [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 4 of 10 cy22050 frequency calculation the cy22050 is an extremely flexible clock generator with up to six individual outputs, gene rated from an integrated pll. there are four variables used to determine the final output frequency. they are: the input ref, the p and q dividers, and the post divider. the three basic formulas for determining the final output frequency of a cy22150-based design are: clk = ((ref * p)/q)/post divider clk = ref/post divider clk = ref the basic pll block diagram is shown in figure 2 . each of the six clock outputs has a total of seven output options available to it. there are six post divider options: /2 (two of these), /3, /4, /div1n, and div2n. div1n and div2n are separately calculated and can be independent of each other. the post divider options can be applied to the calculated pll frequency or to the ref directly. in addition to the six post divi der options, the seventh option bypasses the pll and passes the re f directly to the crosspoint switch matrix. clock output settings: crosspoint switch matrix each of the six clock outputs ca n come from any of seven unique frequency sources. the crosspoint switch matrix defines which source is attached to each individual clock output. although it may seem that there are an unlimit ed number of divider options, there are several rules that must be taken into account when selecting divider options. figure 2. basic pll block diagram table 3. clock output definition clock output divider definition and notes none clock output source is the reference input frequency /div1n clock output uses a generated /div1n option from divider bank 1. allowable values for div1n are 4 to 127. if divider bank 1 is not being used, set div1n to 8. /2 clock output uses a fixed /2 option fr om divider bank 1. if this option is used, div1n must be divisible by 4. /3 clock output uses a fixed /3 option from divider ba nk 1. if this option is used, set div1n to 6. /div2n clock output uses a generated /div2n option from divider bank 2. allowable values for div2n are 4 to 127. if divider bank 2 is not being used, set div2n to 8. /2 clock output uses a fixed /2 option fr om divider bank 2. if this option is used, div2n must be divisible by 4. /4 clock output 2 uses a fixed /4 option from divider ba nk 2. if this option is used, div2n must be divisible by 8. q vco p /2 / 3 / 2 lclk1 lclk2 lclk3 lclk4 clk5 clk6 crosspoint switch ref pfd divider bank 1 / 4 divider bank 2 /div1n /div2n matrix [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 5 of 10 reference crystal input the input crystal oscillator of the cy22050 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference clock source. the oscillator inverter has programmable gain, allowing for maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. the value of the input load capacitors is determined by eight bits in a programmable register. total load capacitance is determined by the formula: capload = (c l ? c brd ? c chip )/0.09375 pf in cyclocksrt, enter the crystal capacitance (c l ). the value of capload is determined automatical ly and programmed into the cy22050. if you require greater control ov er the capload value, consider using the cy22150f for serial configuration and control of the input load capacitors. for an external clock source, the default is 0. input load capacitors are placed on the cy22050 die to reduce external component cost. these capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes. absolute maximum conditions parameter description min max unit v dd supply voltage ?0.5 7.0 v v ddl i/o supply voltage ?0.5 7.0 v t s storage temperature [3] ?65 125 c t j junction temperature 125 c package power dissipation?commercial temp 450 mw package power dissipation?industrial temp 380 mw digital inputs av ss ? 0.3 av dd + 0.3 v digital outputs referred to v dd v ss ? 0.3 v dd + 0.3 v digital outputs referred to v ddl v ss ? 0.3 v ddl +0.3 v esd static discharge voltage per mil-std-833, method 3015 2000 v recommended oper ating conditions parameter description min typ. max unit v dd operating voltage 3.135 3.3 3.465 v vddl hi operating voltage 3.135 3.3 3.465 v vddl lo operating voltage 2.375 2.5 2.625 v t ac ambient commercial temp 0 70 c t ai ambient industrial temp ?40 85 c c load max. load capacitance v dd /v ddl = 3.3v 15 pf c load max. load capacitance v ddl = 2.5v 15 pf f refd driven ref 1 133 mhz f refc crystal ref 8 30 mhz t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms note 3. rated for 10 years. [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 6 of 10 dc electrical characteristics parameter [4] name description min typ. max unit i oh3.3 output high current v oh = v dd ? 0.5v, v dd /v ddl = 3.3v 12 24 ma i ol3.3 output low current v ol = 0.5v, v dd /v ddl = 3.3v 12 24 ma i oh2.5 output high current v oh = v ddl ? 0.5v, v ddl = 2.5v 8 16 ma i ol2.5 output low current v ol = 0.5v, v ddl = 2.5v 8 16 ma v ih input high voltage cmos levels, 70% of v dd 0.7 1.0 v dd v il input low voltage cmos levels, 30% of v dd 00.3v dd i vdd [5,6] supply current av dd /v dd current 45 ma i vddl3.3 [5,6] supply current v ddl current (v ddl = 3.465v) 25 ma i vddl2.5 [5,6] supply current v ddl current (v ddl = 2.625v) 17 ma i dds power down current v dd = v ddl = av dd = 3.465v 50 a i ohz i olz output leakage v dd = v ddl = av dd = 3.465v 10 a ac electrical characteristics parameter [4] name description min typ. max unit t1 output frequency, commercial temp clock output limit, 3.3v 0.08 (80 khz) 200 mhz clock output limit, 2.5v 0.08 (80 khz) 166.6 mhz output frequency, indus- trial temp clock output limit, 3.3v 0.08 (80 khz) 166.6 mhz clock output limit, 2.5v 0.08 (80 khz) 150 mhz t2 output duty cycle duty cycle is defined in figure 4 ; t1/t2 f out > 166 mhz, 50% of v dd 40 50 60 % duty cycle is defined in figure 4 ; t1/t2 f out < 166 mhz, 50% of v dd 45 50 55 % t3 lo rising edge slew rate (v ddl = 2.5v) output clock rise time, 20% ? 80% of v ddl . defined in figure 5 0.6 1.2 v/ns t4 lo falling edge slew rate (v ddl = 2.5v) output clock fall time, 80% ? 20% of v ddl . defined in figure 5 0.6 1.2 v/ns t3 hi rising edge slew rate (v ddl = 3.3v) output clock rise time, 20% ? 80% of v dd /v ddl . defined in figure 5 0.8 1.4 v/ns t4 hi falling edge slew rate (v ddl = 3.3v) output clock fall time, 80% ? 20% of v dd /v ddl . defined in figure 5 0.8 1.4 v/ns t5 [7] skew output-output skew betwe en related outputs 250 ps t6 [8] clock jitter peak-to-peak period jitter (see figure 6 )250ps t10 pll lock time 0.30 3 ms notes 4. not 100% tested, guaranteed by design. 5. i vdd currents specified for two clk outputs running at 125 mhz, two lclk outputs running at 80 mhz, and two lclk outputs running at 66.6 mhz. 6. use cyclocksrt to calculate actual i vdd and i vddl for specific output frequency configurations. 7. skew value guaranteed when outputs are generated from the same divider bank. see logic block diagram for more information. 8. jitter measurement will vary. actual jitter is dependent on xin ji tter and edge rate, number of active outputs, output freque ncies, v ddl (2.5v or 3.3v), temperature, and output load. for more information, refer to the application no te, ?jitter in pll-based systems: causes, effects, and soluti ons,? available at http://www.cypress.com, or contact your local cypress field applications engineer. [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 7 of 10 figure 3. test circuit figure 4. duty cycl e definition: dc = t2/t1 figure 5. rise and fall time definitions figure 6. peak-to-peak jitter 0.1 f v dd 0.1 f av dd clk out c load gnd outputs v ddl 0.1 f t1 t2 clk 50% 50% t3 clk 80% 20% t4 clk t6 [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 8 of 10 ordering information ordering code package type temperature operating range operating voltage cy22050fc [10] 16-lead tssop commercial (0 to 70c) 3.3v cy22050fi [10] 16-lead tssop industrial (?40 to 85c) 3.3v cy22050zc-xxx [9, 10] 16-lead tssop commercial (0 to 70c) 3.3v CY22050ZC-XXXT [9, 10] 16-lead tssop-tape and reel commercial (0 to 70c) 3.3v cy22050zi-xxx [9, 10] 16-lead tssop industrial (?40 to 85c) 3.3v cy22050zi-xxxt [9, 10] 16-lead tssop-tape and reel industrial (?40 to 85c) 3.3v cy3672 [11] ptg development kit cy3672adp000 cy22050f socket cy22050kfc 16-lead tssop commercial (0 to 70c) 3.3v cy22050kfi 16-lead tssop industrial (?40 to 85c) 3.3v pb-free cy220501kfzxi 16-lead tssop with nipdau lead finish industrial (?40 to 85c) 3.3v cy22050fzxc [10] 16-lead tssop commercial (0 to 70c) 3.3v cy22050fzxi [10] 16-lead tssop industrial (?40 to 85c) 3.3v cy22050zxc-xxx [9, 10] 16-lead tssop commercial (0 to 70c) 3.3v cy22050zxc-xxxt [9, 10] 16-lead tssop-tape and reel commercial (0 to 70c) 3.3v cy22050zxi-xxx [9, 10] 16-lead tssop industrial (?40 to 85c) 3.3v cy22050zxi-xxxt [9, 10] 16-lead tssop-tape and reel industrial (?40 to 85c) 3.3v cy22050kfzxc 16-lead tssop commercial (0 to 70c) 3.3v cy22050kfzxi 16-lead tssop industrial (?40 to 85c) 3.3v cy22050kzxc-xxx [9] 16-lead tssop commercial (0 to 70c) 3.3v cy22050kzxc-xxxt [9] 16-lead tssop-tape and reel commercial (0 to 70c) 3.3v cy22050kzxi-xxx [9] 16-lead tssop industrial (?40 to 85c) 3.3v cy22050kzxi-xxxt [9] 16-lead tssop-tape and reel indu strial (?40 to 85c) 3.3v 16-pin tssop pac kage characteristics parameter name value unit ja theta ja 115 c/w complexity transistor count 74,600 transistors notes 9. the cy22050zc-xxx and cy22050zi-xxx are factory-programmed confi gurations. factory programming is available for high-volume d esign opportunities of 100 ku/year or more in production. for more details, contact your local cypress field application engineer or cypress sales represe ntative. 10. not recommended for new designs. 11. 38-07409, cy3672 ptg programming kit [+] feedback
cy22050 cy220501 document #: 38-07006 rev. *f page 9 of 10 package drawing and dimensions figure 7. 16-pin tssop 4.40 mm body z16.173 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05gms 51-85091-*a [+] feedback
document #: 38-07006 rev. *f revised january 21, 2009 page 10 of 10 bp microsystems is a trademark of bp micr osystems. hilo systems is a trademark of hi- lo systems. all prod uct and company names mentioned in this document are the trademarks of their respective holders. cy22050 cy220501 ? cypress semiconductor corporation, 2001-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy22050, cy220501 one-pll gene ral purpose flash-programmable clock generator document number: 38-07006 rev. ecn orig. of change submission date description of change ** 108185 ckn 08/08/01 new data sheet. *a 110054 ckn 03/04/02 changed from preliminary to final. *b 121862 rbi 12/14/02 power up requirements a dded to operating conditions information. *c 310575 rgl 01/20/05 added lead-free devices. *d 314233 rgl 01/31/05 removed the tape a nd reel devices in the non-dash parts. *e 2440826 aesa 05/15/08 updated template. added note ?not recommended for new designs.? and ?38-07409, cy3672 ptg programming kit?. corrected "ftg" to ptg" in ordering information table. added part numbers cy22050kfc, cy22050kfi, cy22050kfzxc, cy22050kfzxi, cy22050kzxc-xxx, cy22050kzxc-xxxt, cy22050kzxi-xxx, and cy22050kzxi-xxxt in ordering information table. changed lead-free to pb-free. *f 2642064 kvm 01/21/09 added cy220501 to title. added cy220501kfzxi to ordering table. [+] feedback
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